| Di seguito sono consultabili le note di rilascio - in gergo "release notes" - relative al file Memtest86 7.0 beta 1, nel caso in cui gli sviluppatori abbiano reso disponibile tale documentazione in occasione della pubblicazione del software. Tuttavia, se hai bisogno di maggiori informazioni su Memtest86 7.0 beta 1, o se le note di rilascio non sono (ancora) disponibili, è comunque possibile procedere con la lettura della descrizione del file. |
New Features
- Row Hammer Test (Test 13) now uses double-sided hammering and random data patterns in an attempt to expose more RAM modules susceptible to disturbance errors. During our testing we observed double sided hammering was effective at high frequencies, but at lower frequencies single sided hammering was more effective. So feedback on this would be good.
- PXE network boot is now fully supported. Configuration file can now be obtained from the server. Report files can also be uploaded to the server. Logging is unavailable.
- Memory tests are run in Parallel CPU mode by default, if supported by the UEFI firmware. Running in parallel mode significantly decreases the test time as compared to running in single CPU mode and should also help to detect more errors faster. This was made possible after developing a work around for UEFI BIOS bug that prevented multi-threading on some machines.
- Added 'HAMMERPAT' config file parameter to specify the data pattern to use for the row hammer test. By default, random data patterns are used.
- Added 'HAMMERMODE' config file parameter to specify whether to use single or double sided hammering. By default, double-sided hammering is used.
- Added 'CPULIST' config file parameter to specify a subset of available CPUs to enable for the memory tests.
- Added 'BGCOLOR' config file parameter to specify the background colour to use
- Added Portuguese translations
- <We are hoping to add to this list before the final release>
Fixes/Enhancements
- Added ECC support for different revisions of Intel Skylake memory controllers
- Fixed ECC detection on Intel Broadwell-H chipsets
- Changed how ECC errors are detected on Broadwell chipsets
- Changed how ECC errors are detected on Atom C2000 chipset
- Added SMBUS (SPD) support for Intel Broxton
- Added SMBUS (SPD) support for Intel Airmont
- Reduced the number of iterations for the Modulo 20 Test (Test 9) to decrease the test time
- Reduced the number of addresses to be hammered for the Row hammer Test (Test 13) to decrease the test time
- When no tests are completed, the test report now displays "N/A" as oppose to "PASS"
- Speeds greater than 10000MB/s are converted to GB/s when displaying memory/cache speeds in the test screen
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